1. Field of the Invention
The present relates generally to semiconductor device fabrication. More particularly, the present invention relates to a silicide process utilizing pre-amorphization implant (PAI) and a second spacer.
2. Description of the Prior Art
As known in the art, silicide such as titanium silicide (TiSi2) is a typical contact material used to reduce contact resistance. It is also known that TiSi2 exists as a C49 phase or as a C54 phase. When using the general processing conditions for forming TiSi2, the less desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required. Besides, the titanium silicide process is flawed because each titanium atom consumes two silicon atoms to form the titanium silicide.
To cope with the difficulties arose due to the use of titanium silicide, nickel (Ni) has been used to replace titanium in the silicide process. FIGS. 1–4 are schematic, cross-sectional diagrams showing the typical nickel silicide process. As shown in FIG. 1, a gate 12 is formed on a substrate 10 with a gate oxide layer 14 interposed therebetween. An offset lining oxide layer 16 is typically formed on the sidewalls of the gate 12 and extends to the main surface of the substrate 10. A pair of silicon nitride spacers 18 is formed on the offset lining oxide layer 16. Source/drain extension regions 22 are formed under the silicon nitride spacers 18. After the formation of the silicon nitride spacers 18, dopants are implanted into the substrate 10 to form source/drain regions 24.
Subsequently, as shown in FIG. 2, a pre-amorphization implant (PAI) 30 is carried out to form an amorphized layer 32. PAI is accomplished by implanting an amorphizing substance such as Ge into the substrate 10 at a tilt angle. The amorphized layer 32 overlaps with the silicon nitride spacer 18.
As shown in FIG. 3, a blanket nickel layer 42 is then sputtered onto the substrate 10. Finally, as shown in FIG. 4, the nickel layer 42 reacts with the substrate 10 and the gate 12 to form nickel silicide layer 52. The un-reacted metal is then removed from the wafer surface by wet etching.
However, it has been discovered that species such as Ge implanted into the substrate 10 during the PAI process easily deactivate the dopants within the source/drain extension regions 22 (extension dopant deactivation), hence degrading the transistor performance. Further, a wet pre-clean process is ordinarily performed before silicidation. The offset lining oxide layer 16 is easily attacked by the wet pre-clean agent, thus causing so-called nickel silicide piping effect.
In light of the above, there is a need to provide an improved method to fabricate a transistor with silicided source and drain without deteriorating the performance of the transistor.